1. Field of the Invention
The invention relates to methods to self-synchronize clocks on multiple chips in a system
2. Background Art
A synchronous digital system consists of multiple chips that run on reference clocks with known relationship. Typically there are cross-chip functions that require the “time-zero” on each chip to be synchronized for the functions to work properly.
In a multi-chip system, such as shown in FIG. 1, to synchronize all chips with each other without external controls, one chip may be temporarily assigned as the “master” chip. The rest of the chips will be “slave” chips. After a system is powered on, the master chip may start to send out synchronization signals to synchronize the “time-zero” of all slave chips and itself. The “time-zero” events usually are repeating with very long cycles. The timing of “time-zero” is typically aligned to the reference clock boundary assuming all chips are receiving the same reference clocks with reasonable skew or known deterministic skew. If all chips are placed close together and a synchronization signal sent from one chip can arrive at another within one reference clock cycle, the “master” chip may simply send out the synchronization signals one reference clock cycle before the intended time-zero. Once the signals arrive at destination chips, all chips can set their “time-zero” to the following rising edge of the reference clock. If the reference clocks for all the chips are not identical, protocols for “time-zero” may be easily determined as long as the relationships and skews among all reference clocks are known. One synchronization signal may be shared among several chips if needed.
In a system with long distances among chips and short reference clock cycle, as shown in FIG. 2, synchronization signals may take multiple reference cycles to reach the destination chips depending on the actual path lengths and packaging/chip process variations. The simple synchronization approach described above no longer guarantee successful synchronization among all chips, since each chip may need different number of reference cycle to receive the synchronization signals. New approaches to account for all possible situations will be required.
Note that in FIG. 3 Chip B and C are not synchronized to the same reference clock cycle.
In a simplified situation, as shown in FIG. 4, all the chips under consideration are still close together and the difference between the maximum and minimum latency for sending synchronization signals from one chip to another may be less than one reference clock cycle with all packaging/chip process variations considered. Additional time may be added prior to sending out synchronization signals so the synchronization signals arrived at all chips within the same reference clock boundaries. But this approach still has the same limitation as the original approach in term of system size and package/process variations. Additional work on package design may be required to match the latencies of synchronization signals among all chips, which may not feasible in larger systems.